AD9652BBCZ-310

The AD9652BBCZ-310 is a high-performance dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high-speed signal processing applications that require exceptional dynamic range over a wide input frequency range, up to 465 MHz.

This ADC features a low noise floor of −157.6 dBFS and a large signal spurious-free dynamic range (SFDR) performance that exceeds 85 dBFS, allowing low-level signals to be resolved in the presence of large signals. The dual ADC cores utilize a multistage, pipelined architecture with integrated output error correction logic to ensure accurate conversions.

The AD9652BBCZ-310 incorporates a high-performance on-chip buffer and internal voltage reference, simplifying the interface to external driving circuitry while preserving the exceptional performance of the ADC. It can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle.

The 16-bit output data (with an overrange bit) from each ADC is interleaved onto a single LVDS output port along with a double data rate (DDR) clock. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9652BBCZ-310 is available in a 144-ball CSP_BGA package and is specified over the industrial temperature range of −40°C to +85°C.

With its integrated dual, 16-bit, 310 MSPS ADCs, on-chip buffer, and support for LVDS outputs, the AD9652BBCZ-310 is an ideal choice for applications such as military radar and communications, multimode digital receivers (3G or 4G), test and instrumentation, and smart antenna systems. Its high dynamic range, low noise, and excellent SFDR performance make it well-suited for high-speed signal processing tasks that require precise and accurate analog-to-digital conversion.